A recent development in integrated circuit testing is the use of the JTAG (Joint Test Action Group) test port for in-situ testing of integrated circuit (IC) chips mounted on a board. This standard has been adopted by the Institute of Electrical and Electronics Engineers (IEEE) and is now defined as IEEE Standard 1149.1-1990. The IEEE Std 1149.1 is described in "The Test Access Port and Boundary-Scan Architecture" (IEEE Computer Society Press. 1990), incorporated herein by reference.
FIG. 1 schematically shows a memory interface device with JTAG circuit (in accordance with IEEE Std 1149.1). Reference numerals 2 and 4 represent the memory interface chip with the JTAG circuit and a DRAM device chip, respectively. The JTAG circuit comprises three principal components: a Test Access Port (TAP) controller 10, an instruction register (IR) portion 20, and a boundary-scan register or data register (DR) portion 30. The instruction register portion 20 consists of an instruction register 21, an instruction decoder 22, and a multiplexer 23. The boundary-scan register portion 30 consists of a bypass register 32, a boundary-scan register 33 postioned at the perimeter of, or otherwise surrounding an application core logic 31 of, the interface device chip 2, and a multiplexer 34. As can be seen in FIG. 1, the JTAG circuit includes three inputs: a test clock (TCK), a test mode select (TMS), and a test data input (TDI); and one output, test data out (TDO).
Implementation of JTAG boundary-scan testing requires that, in addition to its normal application logic, each integrated circuit chip be fabricated with circuits known as Boundary-Scan Cells shown in FIG. 2. A boundary-scan cell consists of two multiplexers 51, 54, and two flip-flops 52, 53, referred to respectively as "capture" and "update" flip-flops. Each boundary-scan cell includes two data inputs: a normal data input (NDI) and a serial data input (SDI); and two data outputs: a normal data output (NDO) and a serial data output (SDO). The boundary-scan cells are interconnected to form a scan path between the test data input TDI and test data output TDO of the application IC. Each boundary-scan cell is coupled between the application logic and one of the functional input and output pins of the integrated circuit such that each functional input and output pin is coupled to a separate one of a normal data input and normal data output respectively of the boundary-scan cell.
During normal IC operation, input and output signals pass freely through each boundary-scan cell, from the normal data input NDI, to the normal data output NDO. When the boundary-test mode is activated, the boundary of the integrated circuit is controlled in such a way that a test stimulus can be shifted in and applied to each boundary-scan cell input NDI, and a test response can be captured at each boundary-scan cell output NDP and shifted out for inspection.
FIG. 3 is a state diagram of the TAP controller 10 of FIG. 1. The TAP controller 10, driven by the TCK input, responds to the TMS input as shown. The state diagram consists of six steady states: Test.sub.-- Logic.sub.-- Reset, Run.sub.-- Test/Idle, Shift.sub.-- DR, Pause.sub.-- DR, Shift.sub.-- IR, and Pause.sub.-- IR. A unique feature of this protocol is that only one steady state exists for the condition when TMS is set high: the Test.sub.-- Logic.sub.-- Reset state. This means that a reset of the test logic can be achieved within five TCK clock cycles or less by setting the TMS input high.
At power up, or during normal operation of the host IC, the TAP is forced into the Test.sub.-- Logic.sub.-- Reset state by driving TMS high and applying five or more TCK clock cycles. In this state, the TAP issues a reset signal that places all test logic in a condition that does not impede normal operation of the host IC. When test access is required, a protocol is applied via the TMS and TCK inputs, causing the TAP to exit the Test.sub.-- Logic.sub.-- Reset state and change to the appropriate state. From the Run.sub.-- Test/Idle state, an instruction register scan or a data register scan can be issued to transition the TAP through the appropriate states shown in FIG. 3.
The states of the data register scan and instruction register scan columns are mirror images of each other, adding symmetry to the protocol sequences. This first action that occurs when either block is entered is a capture operation. For the data registers, the Capture.sub.-- DR state is used to capture (or parallel load) the data into the selected serial data path. If the BSR is the selected data register, the normal data inputs (NDIs) are captured during this state. In the instruction register, the Capture.sub.-- IR state is used to capture status information into the instruction register.
From the Capture state, the TAP transitions to either the Shift or Exit1. Normally, the Shift state follows the Capture state so that test data or status information can be shifted out for inspection and new data shifted in. Following the Shift state, the TAP either returns to the Run.sub.-- Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The reason for entering the Pause state is to temporarily suspend the shifting of data through either the selected data register or instruction register while a required operation is performed, such as refilling a tester memory buffer. From the Pause state, shifting can resume by re-entering the Shift state via the Exit2 state or be terminated by entering the Run.sub.-- Test/Idle state via the Exit2 state via the Exit2 and Update states.
Upon entering the data register scan or instruction register scan columns, the data being shifted into the selected scan path is not output until the TAP enters the Update.sub.-- DR or Update.sub.-- IR state. In the Update state, the new data being shifted into the selected scan path is updated.
Examples of contemporary boundary-scan testing techniques are disclosed in U.S. Pat. No. 5,029,166 for Method And Apparatus For Testing Circuit Boards issued to Jarwala et al., U.S. Pat. No. 5,155,732 for Method And Apparatus For Data Transfer To And From Devices Through A Boundary-Scan Test Access Port issued to Jarwala et al., U.S. Pat. No. 5,355,369 for High-Speed Integrated Circuit Testing With JTAG issued to Greenberger et al., and U.S. Pat. No. 5,636,227 for Integrated Circuit Test Mechanism And Method issued to Segars, the contents of all of which are incorporated herein by reference.
During a debugging operation, a program must be checked for errors or other types of malfunctioning. Program tracing is the most commonly used technique in program debugging, which is representative of the stream of instructions executed by a microprocessor. By examining the instruction stream that was executed, a programmer may determine if the application hardware and software are performing properly. If unintended behavior of the hardware or software is detected, the programmer may successively record all addresses in order to determine what caused the behavior. This recording can be done, either by monitoring the internal bus directly, or by temporarily logging such addresses for subsequent outputting and checking. Often, such procedures either consume a great deal of time in a step-by-step operation, or alternatively, require extensive external accessibility through a large amount of additional microprocessor pins. Both approaches are expensive. Moreover, it is difficult to organize execution of such monitoring in real time in view of the enormous amount of data produced.